|
Fluke 280/290
Series Informational Tour
|
Variable clock architecture for ARBs avoids the limitations of DDS
|
|
|
Recently DDS (direct digital synthesis) based function generators have been developed into arbitrary/function generators with impressive specifications.
|
|
|
However, the DDS approach to arbitrary waveform generation imposes serious limitations which are not immediately obvious.
The alternative approach of a variable clock architecture offers a greater level of flexibility and can be used to solve many more real-world problems.
Some manufacturers, who offer both types of generator, refer to DDS arbitrary generators as AFGs (arbitrary function generators) and to variable clock generators as AWGs (arbitrary waveform generators). Other manufacturers give no indication of the technology used for arbitrary waveform generation.
|
|
|
Before purchasing a generator intended for arbitrary waveform use, it is important to discover which technology it uses.
|
|
Evolution of the technology
|
|
|
The early arbitrary waveform generators used a variable frequency clock to replay the waveform stored in RAM at the required repetition rate.
|
|
|
In this simple system, the waveform repetition frequency is equal to the clock frequency divided by the number of waveform points.
All of the waveform points within the RAM are played out on every cycle.
|
|
These basic variable clock systems rapidly evolved to include memory segmentation and sequencing.
|
|
|
By dividing the memory into segments, far more complex arbitrary waveforms could be constructed by repeating individual waveform elements within a sequence.
This technique greatly increased the capabilities of the arbitrary generator.
|
|
Waveform sequencing is only available on generators with a variable clock architecture. DDS based arbitrary generators have no segmentation and sequencing capability.
|
|
DDS - Direct Digital Synthesis
|
|
DDS (direct digital synthesis) was originally developed for producing high quality sine waves.
|
|
|
In a DDS generator the RAM address increment rate is determined from a fixed clock frequency by a digital block comprising a phase increment register and a phase accumulator.
A description of the DDS technique is available here: DDS Technical (click to show)
|
|
In a DDS generator the RAM address increment rate is determined from a fixed clock frequency by a digital block comprising a phase increment register and a phase accumulator.
A description of the DDS technique is available here: DDS Technical (click to hide)
|
|
The RAM is loaded with the amplitude values of the individual points of one cycle (360 degrees) of the desired waveform (e.g. a sinusoid). Typically the number of points used will be made equal to or greater than the number of vertical amplitude points.
Example for 12-bit system with a 4096 word waveform store, Fmax. of 40MHz & resolution of 0.0001Hz.
One complete cycle of the selected waveform is stored in RAM as 4096 12-bit amplitude values. As the RAM address is incremented the waveform values are output sequentially to the DAC which reconstructs the waveform as a series of voltage steps. Sinewaves and triangles are subsequently filtered to smooth the steps in the DAC output.
The frequency of the output waveform is determined by the rate at which the RAM addresses are changed; in a DDS system the address changes are generated as follows.
The RAM contains the amplitude values of all the individual points of 1 cycle (360°) of the waveform; each sequential address change corresponds to a phase increment of the waveform of 360°/4096. Instead of using a counter to generate sequential RAM addresses, a phase accumulator is used to increment the phase.
On each clock cycle the phase increment, which has been loaded into the phase increment register by the CPU, is added to the current result in the phase accumulator; the 12 most significant bits of the phase accumulator drive the RAM address lines. The output waveform frequency is now determined by the size of the phase increment at each clock. If each increment is the same size then the output frequency is constant; if it changes, the output frequency changes but with phase continuity.
The example uses a 40-bit accumulator and a clock frequency which is 240 x 10-4 (~109·951MHz); this yields a frequency resolution (corresponding to the smallest phase increment) of Fclk/240 = 0·1mHz.
Only the 12 most significant bits of the phase accumulator are used to address the RAM. At a waveform frequency of Fclk/4096 (~27kHz) the RAM address increments on every clock. At all frequencies below this (i.e. at smaller phase increments) one or more addresses are output for more than one clock period because the phase increment is not big enough to step the address at every clock. Similarly at waveform frequencies above 27kHz the larger phase increment causes some addresses to be skipped, giving the effect of the stored waveform being ‘sampled’; different points will be sampled on successive cycles of the waveform.
The minimum number of points required to accurately reproduce a waveshape will determine the maximum useful output frequency: fmax = Fclk/No. of points. For sinewaves a suitably designed filter permits the waveform to be reproduced accurately towards the Nyquist limit (Fclk/2), although because of practical limitations to the filter performance, a lower limit may be set (e.g. 40MHz for a 110MHz clock).
For other waveforms, the required number of points depends upon the complexity of the waveform, the edge speed and transition speed, and the precision with which it must be reproduced.
|
|
Most digital function generators now use DDS which has been further developed into a system for arbitrary waveform generation. Unless stated otherwise, a typical arbitrary/function generator will use DDS for all its waveforms including arbitrary.
|
|
DDS - Advantages and Disadvantages
|
|
Advantages
|
- Frequency Resolution
Long word length phase accumulator can provide frequency resolution to sub micro-hertz levels.
(In a variable-clock arbitrary system, frequency resolution is defined by the clock generator which could itself use DDS).
- Digital Modulation
Modulation words can be added to the phase accumulator to provide digital modulation.
(Direct digital modulation is not possible in a variable-clock arbitrary system).
- Automatic down-sampling
Waveforms are automatically truncated by sampling to allow repetition rates above Fclk / Waveform length.
(In a variable-clock arbitrary system, waveform frequency always equals Fclk / Waveform length. When Fclk is at maximum, shorter waveforms must be used to obtain higher frequency).
|
|
Disadvantages
|
- Waveform Jitter
Only frequencies equal to the clock frequency divided by the waveform length (and sub multiples) are un-sampled. All other frequencies are up-sampled or down-sampled resulting in missing samples and/or jitter.
(A variable-clock arbitrary system is inherently free of sampling jitter).
- No Sequencing Capability
Only a single waveform can be generated at a time. Memory segmentation and waveform sequencing is not possible.
(Most variable-clock arbitrary systems incorporate extensive facilities for waveform segmentation and sequencing).
- No External ARB clock
DDS generators can not use a variable external clock to clock out the waveform.
(DDS generators use a fixed frequency clock. Although this can be locked to an external signal, an external signal can not be used to clock out the arbitrary waveform. Some variable-clock arbitrary systems allow use of a fully variable external ARB clock).
|
|
Many real-world arbitrary waveform requirements can not be fully met using a DDS generator.
|
|
Sampling Error and Jitter - the "achilles heel" of DDS
|
|
|
Recently DDS (direct digital synthesis) based function generators have been developed into arbitrary/function generators with impressive specifications.
However, the DDS approach to arbitrary waveform generation imposes serious limitations which are not immediately obvious.
Whereas a variable clock arbitrary system always plays every waveform sample in sequence, a DDS generator achieves a particular repetition frequency by over-sampling or under-sampling the waveform.
This has important and undesirable effects.
|
Mindful of the maximum sampling frequency and the required repetition rate, the user creates an approximation of the required waveform using 50 points.
|
|
Consider the generation of a "glitched" sine wave at a variable frequency between (say) 900kHz and 1.1MHz.
Compare two generators, both with a maximum sampling rate of 100MS/s, but one using variable clock and the other DDS.
Consider how the two types of generator create the variable frequency output waveform.
In the variable clock generator, the complete waveform is played out using a clock frequency varying between 45MHz and 55MHz. The waveform looks the same regardless of frequency and the glitch width is always 1/50th of the waveform period.
|
|
Continuous oscilloscope capture of
the above waveform run on a
variable clock generator.
|
Expanded version. The glitch is
completely jitter free and is
of constant width.
|
|
|
The variable clock architecture creates waveforms free of Sampling Error and Jitter.
|
|
|
Note that the waveforms shown are being replayed with the Bessel output filter turned off. With the filter on, the sine wave steps would be almost eliminated but the glitch would also be attenuated. See below.
|
|
|
In the DDS generator, the clock always runs at 100MS/s and the frequency variation is created by changing the clock increment.
At exactly 1MHz, the output will be created from identical pairs of sample points occurring 50 times per cycle. However, at other frequencies, the number of 10ns sample points needed to create the required waveform period is no longer integer.
To overcome this, the generator produces different numbers of samples on each cycle of the waveform so as to create the correct average period.
|
Note: Because the oscilloscope is being triggered on the leading edge of the glitch, the jitter appears to be only on the trailing edge.
Actually, the same 10ns of jitter is present on every sample point of the waveform.
|
|
|
Although this has little effect on the shape of the sine wave, it has a major effect on the glitch. The glitch width which at (say) 950kHz, should be 21.05ns, varies continuously between 20ns and 30ns.
|
|
Continuous oscilloscope capture of
the above waveform run on a
DDS generator.
|
Expanded version. The glitch
width is normally 20ns but is
occasionally increased to 30ns.
|
|
|
This jitter is the effect of DDS sampling error.
It will be present for all waveform repetition periods which are not an integer multiple of the clock period times the waveform length.
|
|
|
Now consider what would happen if the required waveform frequency was doubled (range 1.8MHz to 2.2MHz).
In the variable clock generator, the maximum frequency is limited to 2MHz (50 samples of a 100MHz clock). To get up to 2.2MHz, the user must recreate the waveform using 45 points or less. Having done this, the waveform can be produced exactly as before.
|
|
|
|
In the DDS generator, the waveform can remain defined within 50 points because the sampling will automatically reduce the effective number of points in the waveform.
However, above 2MHz the waveform is being under-sampled. In these circumstances the glitch width, which should be just under 10ns, varies continuously between 10ns and Zero.
Missing glitch on one cycle of the waveform.
|
|
Continuous oscilloscope capture of
the above waveform run on a
DDS generator, with
under-sampling occuring.
|
Single-shot oscilloscope capture
of two successive cycles
from the DDS generator showing
one which omits the
glitch altogether.
|
|
|
Missing events.
Once the DDS generator is in under-sampling mode, the sampling error can cause an event to be missed on a particular waveform cycle.
|
|
Waveform Sequencing - a simple example
|
|
|
Waveform sequencing is an important technique which is only available on variable clock architecture generators.
|
|
|
In this simple example the requirement is for a waveform containing three sinewave bursts, each of a different length, followed by an exponential decay. The delay between bursts is also unequal.
By using sequencing, the complete arbitrary waveform can be constructed simply and quickly from three basic arbitrary waveforms - a single cycle sinewave (W1), a decaying sinewave (W2), and a short dc level (W3). These base waveforms could be taken from a library of standard waveshapes.
A nine step sequence is constructed: W1x N1 > W2 > W3 x D1 > W1 x N2 > W2 > W3 x D2 > W1 x N3 > W2 > W3 x D3.
N and D are loop counts for the sequence (i.e. the number of times that the waveform is repeated before the sequence steps on). N defines the sine burst count while D defines the delay. By making the dc level (W 3) very short, the delay time can be defined to a high accuracy. Changes to the waveform, such as variations in the delays, can now be managed with ease (changing a loop count can be done by simply selecting the value and rotating a spin wheel on the generator).
DDS based arbitrary generators can not segment and sequence the waveform memory.
On a DDS based generator, it would be necessary to construct the waveform using PC software.
Even a small change would require the complete waveform to be regenerated and downloaded again. |
|
Sequence Trigger - a powerful additional facility
|
|
|
Example:
A remote system is operated via a serial link and responds to coded pulse streams. The user needs to investigate the system integrity in the presence of noise, and to evaluate its ability to correctly decode a command immediately following the system coming out of "sleep". Upon wake up, the system pulls the control line true. The delay between sending the "wake up" code and the system activation is variable and unknown.
|
|
The user creates two separate waveform segments for the wake-up pulse sequence (W1) and a command pulse sequence (W2). A third waveform segment of a short dc level is also created (W3). The return control line is used to operate the Sequence Trigger on the generator.
|
|
|
|
The user sets up a sequence of:
1 x W1 > W3 repeat until Trigger Event > N x W3 > 1 x W2 where N defines the length of the delay between the system waking up and the command pulses being sent. The output is summed with a noise signal and the results observed subject to varying delays.
This capability is beyond the scope of DDS based arbitrary generators.
|
|
Using sequencing to increase the effective memory length
|
|
|
Example:
The user needs to generate a one-shot waveform of five seconds duration. To achieve sufficient resolution, they need a sampling rate of at least 1MS/s. To create this as a single waveform would require 5 million points of waveform memory.
|
|
|
However, the waveform is not truly random and includes repeated waveform elements and periods of inactivity (dc levels). By segmenting the waveform, all of the individual elements can be created using less than 50 thousand points (a dc level takes up virtually no space).
|
|
|
|
The five second waveform is created by defining a sequence in which the waveform segments are output in a defined order and subject to individual repeat counts each time.
By this means the "effective" waveform length is dramatically increased (by a factor of one hundred in this case).
A DDS based arbitrary generator would have to use a dramatically lower resolution (sampling rate) in order to contain the whole waveform within its waveform memory.
|
|
External ARB clock - true synchronism with external signals
|
|
|
Example:
The user needs to simulate the response of a transducer within an electro-mechanical system. The output signal of the transducer is directly related to a clock signal within the system, which can vary over a wide range.
|
|
|
In a variable clock generator, it is potentially possible to drive the arbitrary generation system directly from an external clock. In this way the waveform is generated in perfect synchronism with the external clock regardless of frequency, phase, or clock interruption.
Note:
An External Arbitrary Clock input is a different facility from an external system clock input.
Most generators have an external clock input and a waveform trigger input.
This allows the generator's fixed internal clock to be synchronised with an external clock within a narrow frequency band (e.g. +/- 2%), and for the waveform to be started synchronously with an external event.
However, this does not provide synchronism of the actual sample points.
A DDS based arbitrary generator can not use an External ARB clock. There is no simple direct relationship between the waveform sample points and the clock within a DDS generator.
|
|
Universal Architecture - combining DDS and Variable Clock
|
|
|
The most sophisticated generators combine variable clock and DDS architectures within the same instrument.
Variable clock is used for generating most arbitrary waveforms, while DDS is used for generating standard waveforms such as sine waves.
The advantages of variable clock generation for arbitrary waveform have been explained earlier.
|
|
|
However, the DDS system has important advantages when frequency Sweep or other frequency modulation is required, because it offers better frequency agility and automatic control of the effective waveform length.
Universal architecture offers the best possible performance by incorporating the advantages of both variable clock and DDS architectures within the same instrument.
|
|
|
Discovering the architecture type - interpreting the data sheet
|
|
Before purchasing a generator intended for arbitrary waveform use, it is important to discover which technology it uses.
Some manufacturers, who offer both types of generator, refer to DDS arbitrary generators as AFGs (arbitrary function generators) and to variable clock generators as AWGs (arbitrary waveform generators).
|
|
|
However, other manufacturers give no indication of the technology used for arbitrary waveform generation.
|
|
The most direct way of establishing the arbitrary generation architecture it to look for references to Waveform Sequencing within the arbitrary waveforms sections of the specifications.
|
|
If there is no reference to Waveform Sequencing within the specifications, it is highly likely that the generator uses DDS for arbitrary waveform generation and will suffer the disadvantages explained earlier.
|
|
|
Fluke Universal Waveform Generators - the complete solution
|
The 280 and 290 series generators from Fluke use a "universal" architecture which combines variable clock generation of arbitrary waveforms and DDS generation of standard waveforms such as sine waves.
Both series are available with 1, 2 or 4 channels.
The 290 series offers 100MS/s maximum sampling with 1M word waveform memory, sine waves to 40MHz and an external ARB clock input.
Both series include full waveform sequencing.
Pulse generation is covered by a full pulse train editor which allows sequences of up to ten pulses with varying width, delay, amplitude and offset to be defined.
The generators are all supplied complete with a copy of Waveform Manager Plus. This Windows based program provides comprehensive waveform creation, editing and conversion facilities.
|
|
|
These Fluke generators offer the most powerful internal architecture for arbitrary waveform generation, allowing them to solve more "real world" problems.
|
|
|
Waveform Manager Plus - the complete solution for creating arbitrary waveforms
|
|
|
Waveform Manager Plus provides full Windows based creation and editing and has full waveform building tools including standard waveforms, mathematical expressions, and freehand drawing.
It provides horizontal resolutions to > 1 million points and vertical resolutions to 16 bits.
|
|
|
It supports waveform import & export via clipboard, and can use RS232, GPIB or USB interfaces transfer to or from the generator.
|
|
|
|
;)
;)
;)
;)
;)
;)
;)
;)
;)
;)
;)
;)
;)
;)
;)
;)
;)
;)
;)
;)
;)
;)
;)
;)
;)
;)
;)
